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1/11 march 2005 STD70NH02L n-channel 24v - 0.0062 ? - 60a ipak/dpak stripfet? iii power mosfet rev. 4.0 figure 2: internal schematic diagram figure 1: package table 1: general features typical r ds (on) = 0.0062 ? @ 10 v typical r ds (on) = 0.008 ? @ 5 v r ds(on) * qg industry?s benchmark conduction losses reduced switching losses reduced low threshold device in compliance with the 2002/95/ec european directive through-hole ipak (to-251) power package in tube (suffix ?-1") surface-mounting dpak (to-252) power package in tape & reel (suffix ?t4") description the STD70NH02L utilizes the latest advanced design rules of st?s proprietary stripfet? technology. this is suitable fot the most demanding dc-dc converter application where high efficiency is to be achieved. applications specifically designed and optimised for high efficiency dc/dc convertes table 2: ordering information type v dss r ds(on) i d STD70NH02L 24 v < 0.008 ? 60 a(*) sales type marking package packaging STD70NH02Lt4 d70nh02l to-252 tape & reel STD70NH02L-1 d70nh02l to-251 tube 3 2 1 1 3 ipak to-251 (suffix ?-1?) dpak to-252 (suffix ?t4?) table 3: absolute maximum ratings symbol parameter value unit v spike(1) drain-source voltage rating 30 v v ds drain-source voltage (v gs = 0) 24 v v dgr drain-gate voltage (r gs = 20 k ? ) 24 v v gs gate- source voltage 20 v i d (*) drain current (continuous) at t c = 25c 60 a i d drain current (continuous) at t c = 100c 50 a i dm (2) drain current (pulsed) 240 a p tot total dissipation at t c = 25c 70 w derating factor 0.47 w/c e as (3) single pulse avalanche energy 360 mj t stg storage temperature -55 to 175 c t j max. operating junction temperature
STD70NH02L 2/11 table 4: thermal data electrical characteristics (t case = 25 c unless otherwise specified) table 5: off table 6: on (4) table 7: dynamic rthj-case rthj-amb t l thermal resistance junction-case thermal resistance junction-ambient maximum lead temperature for soldering purpose max max 2.14 100 275 c/w c/w c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 25 ma, v gs = 0 24 v i dss zero gate voltage drain current (v gs = 0) v ds = 20 v v ds = 20 v t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 11.8 v r ds(on) static drain-source on resistance v gs = 10 v i d = 30 a v gs = 5 v i d = 15 a 0.0062 0.008 0.008 0.014 ? ? symbol parameter test conditions min. typ. max. unit g fs (4) forward transconductance v ds = 10 v i d = 18 a 27 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 16v f = 1 mhz v gs = 0 2050 545 70 pf pf pf r g gate input resistance f = 1 mhz gate dc bias = 0 test signal level = 20 mv open drain 1 ?
3/11 STD70NH02L table 8: switching on table 9: switching off table 10: source drain diode (1) garanted when external rg=4.7 ? and t f < t fmax . (4) pulsed: pulse duration = 300 s, duty cycle 1.5 %. (2) pulse width limited by safe operating area (5) q oss = c oss * ? v in , c oss = c gd + c ds . see appendix a ( 3 ) starting t j = 25 o c, i d = 25a, v dd = 15v (*) value limited by wire bonding . . symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 10 v i d = 30 a r g = 4.7 ? v gs = 5 v (resistive load, figure 17) 12 200 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 10 v i d = 60 a v gs = 5 v 17 7.7 3.5 22 nc nc nc q oss (5) output charge v ds = 10 v v gs = 0 v 14 nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 10 v i d = 30 a r g = 4.7 ?, v gs = 5 v (resistive load, figure 17) 18 25 33 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm source-drain current source-drain current (pulsed) 60 240 a a v sd (4) forward on voltage i sd = 30 a v gs = 0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 60 a di/dt = 100a/s v dd = 15 v t j = 150c (see test circuit, figure 19) 36 65 3.6 ns nc a electrical characteristics (continued) figure 3: safe operating area figure 4: thermal impedance
STD70NH02L 4/11 figure 5: output characteristics figure 6: transfer characteristics figure 7: transconductance figure 8: static drain-source on resistance figure 9: gate charge vs gate-source voltage figure 10: capacitance variations
5/11 STD70NH02L figure 11: normalized gate threshold voltage vs temperature figure 12: normalized on resistance vs temperature figure 13: source-drain diode forward characteristics figure 14: normalized breakdown voltage vs temperature .
STD70NH02L 6/11 figure 15: unclamped inductive load test circuit figure 17: switching times test circuits for resis- tive load figure 16: unclamped inductive waveform figure 18: gate charge test circuit figure 19: test circuit for inductive load switching and diode recovery times
7/11 STD70NH02L dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.9 0.025 0.035 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 9.35 10.1 0.368 0.397 l2 0.8 0.031 l4 0.6 1 0.023 0.039 == d l2 l4 1 3 == b e == b2 g 2 a c2 c h a1 detail "a" a2 detail "a" to-252 (dpak) mechanical data 0068772-b
STD70NH02L 8/11 dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a3 0.7 1.3 0.027 0.051 b 0.64 0.9 0.025 0.031 b2 5.2 5.4 0.204 0.212 b3 0.85 0.033 b5 0.3 0.012 b6 0.95 0.037 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 15.9 16.3 0.626 0.641 l 9 9.4 0.354 0.370 l1 0.8 1.2 0.031 0.047 l2 0.8 1 0.031 0.039 a c2 c a3 h a1 d l l2 l1 1 3 = = b3 b b6 b2 e g = = = = b5 2 to-251 (ipak) mechanical data 0068771-e
9/11 STD70NH02L *on sales type
STD70NH02L 10/11 table 11: revision history date revision description of changes march 2005 4.0 added package ipak
11/11 STD70NH02L i nformation furnished is believed to be accurate and reliable. ho wever, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subje ct t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are n ot a uthorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco -singapore - spain - sweden - sw itzerland - united kingdom - united states of america. www.st.com

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